Generally, semiconductor devices, such as, memory may comprise a floating-gate device. Floating-gate devices may comprise a floating gate or charge-trap node to store charge. Poor etch selectivity between an etchant and an inter-gate dielectric formed on the floating gate may result in poor etch profiles, microloading effects, and/or poor etch uniformity across multiple structures.
It will be appreciated that for simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.